Posts

Showing posts from November, 2024

Incompetent coders - the frustration of using Vivado to build FPGA designs

IDIOT SOFTWARE MUST BE RESTARTED CONSTANTLY TO SEE INPUT FILE CHANGES When I update a source file, often Vivado is somehow working from a cached copy and never notices the changes. It is highly frustrating to fix an issue, rerun a Linter or Synthesis and get the same old errors. The only solution is to shut Vivado down and restart. I remember hitting this many times in past years as I worked with the toolchain, but it has changed from sporadic to nearly constant failure to see the changed timestamp. I can't be the only person running the toolchain under Windows, yet this kind of bumbling misperformance has been a feature for years. 

Working on ways to manufacture SLT card sockets and SLT board receptacles

Image
IBM SLT SYSTEM USES .125" PITCH PIN SEPARATION IN A GRID ON THE BOARD The board is divided vertically and horizontally in 1/8" steps, with a hole drilled in the intersection of each horizontal and vertical step On the board (IBM's name for a backplane) a gold plated pin is inserted through the hole at specific locations to form the pattern of 2 rows of 12 pins each where an SLT card can be inserted.  Black dots are pins The SLT board is organized with each card slot consisting of 14 vertical steps 1-14 and five horizontal steps A-E. An SLT card has pins that fit into rows 2 to 13, in columns B and D. Thus the spacing is .125" between pins in a row and .25" between rows. I haven't found an IBM published diameter for the pin, so I will have to measure one at my workshop.  On the card, springy contacts are soldered onto the PCB and are pushed toward the board by the pins of the SLT board as the card is inserted. There is a molded black plastic housing around th...