Memory working, power supply load tested, narrowing in on issue with the A board

MEMORY WORKS CORRECTLY ON THE EDUC-8

I can deposit values into selected memory locations and see the properly when I go back and do an examine of the location. I set up a short program or two which executed properly (except for the A board issue below). 

ACCUMULATOR BOARD PROBLEM

The A board houses the accumulator. The EDUC-8 is a bit serial machine, so that a 'bus' is a single signal with multiple open collector sources. The machine has four of these - A bus, B bus, C bus and D bus - which are used as source and output of bit streams at various points during execution.

The accumulator (AC) register is constructed a shift register, given the bit serial nature of this machine. The input to the shift register is the A bus and when it is clocked it shifts in the bits to update the AC. The logic on the A board determines when pulses are applied to the shift register to cause it to update from the A bus. 

The updates should be during execution phases of instructions that are changing the accumulator, for example when adding numbers together. The addition itself is done with the adder on the P board but the output of the addition is put on the A bus so that it can be clocked into the AC. 

Another register, the program counter (PC) is changed by shifting in new contents during the execution phase (or execution phase of a jump or skip type instruction). The process of incrementing the PC takes place during the fetch stage of instruction execution, making use of A bus among others. The newly computed value should only be shifted into the PC register.

What I observe on my machine is that during the fetch stage, as the PC is updated, the same bits are shifting into the AC. This should not happen; it should only be changed during execution stages. The result is that each instruction wipes out the AC register and leaves it with the new PC value. Thus, programs that want to load a value in AC in an instruction and then update in it subsequent instructions will not work because the original value is overlaid. 

SNAPSHOT OF THE AC REGISTER

The AC register has a mode input (RAL) that is activated to cause a shift of the bits one position to the left, using the parallel load mode of the 74LS95 shift register chips when the T1 signal finishes at the start of an execution cycle. Thus, when it is a RAL instruction, the execution phase does the shift left.

Otherwise, the mode input has the register shift all bits to the right one position when the CPA clock input is pulsed. The A bus feeds a new bit into the leftmost position during that shift operation. This is the normal method of updating the AC, producing eight pulses on CPA to shift in serially the bits from the A bus. 

Both methods of updating the AC should only occur during the execution phase of an instruction. RAL is only active from the decoder (D) board when in execute stage with the RAL operation code. CPA is generated on the A board and should only pass the pulses during execution phases and specific conditions that will update the AC. 

The logic that produces the CPA pulses at the left of the diagram above is driven by the master clock pulses (MCP) based on the various conditions on the right. Moving from right to left to evaluate these, starting with gate A:

1. In execute stage of Twos Complement Add, Increment AC or Complement AC operation codes at times T2 thru T9 (creating eight pulses)
2. In execute stage of Rotate Accumulator Right operation code at time T13
3. One of the conditions of gate B

Gate B simply passes on the eight pulses of times T2 to T9 when the conditions of gate C are met.

Gate C causes the activation if we are executing a Clear Accumulator operation code or if any of the conditions of gate D are met.

Gate D conditions are any of:

• Executing a Deposit and Clear Accumulator op code
• Executing an AND operation code
• Executing an Input-Output Transfer shift function

This is a bit convoluted because some operation codes are examined early, in gate D, while others are examined in C or A. However, in almost every case we get eight pulses at times T2 to T9 except for a single pulse at T13 for a Rotate Accumulator Right instruction. 

These eight pulses take place for  DCA, TAD, IAC, CMA, AND or IOT-shift operation codes during their execute phases. In no situation should one of these signals be active during the fetch stage of an instruction. 

The front panel of the EDUC-8 shows the major instruction op codes with LEDs so I know that DCA, TAD, OPR and IOT are not active. OPR has subinstructions CMA, CLA, RAR, RAL and IAC. But I can't directly observe those signals to verify that when OPR is not active, the related codes are not. Similarly, while the IOT op code is not active, I can't verify that the subinstruction IOT-shift is not active by reference to LEDs. 

DIAGNOSTIC PLAN

I will tack wires to observe the signals in and out of gate A and based on what I see, move back through B, C and D until I figure out what conditions are triggering the pulses to pass through to serially load the AC shift register. 

POWER SUPPLY TESTING, VOLTAGE A BIT LOW

I wired up my 10V AC transformer to the power supply board I constructed, then wired the output to my electronic load to observe the voltage under various loads. The supply plan for the original EDUC-8 was able to provide up to 6A of +5V to the system, with up to 3A said to be required for the EDUC-8 itself and the other 3A available for peripherals I have not yet built.

Given the change from original TTL parts (e.g. 7400) to the low power Schottky versions (e.g. 74LS00), the demands of the CPU will be considerably lower but the power supply ran with very little sag up to almost 4A so it will be completely satisfactory for this machine and its peripherals.

One issue, however, was that the regulated voltage was about 4.8V rather than the desired 5V. I will review the circuit and make changes to bring it up to the target of 5V.

NEED TO BUILD THE CROWBAR CIRCUIT

The plans and schematics for the modern LS version have a crowbar circuit specified, but no PCB to build it was produced in the set of boards I bought. It is simple enough, a 5.6V Zener diode, resistor, capacitor and twin SCRs to short the output when the power supply exceeds 5.6V. I can wire this on some kind of perfboard or other mounting.