Potential substitute for core memory module using SRAM

INTERFACING TO THE IBM 1130 IS SUPER EASY

The IBM 1130 drives four control signals to the core memory module, plus 16 data bits out and 12 to 15 address bits depending on the machine configuration. It also receives 16 bits of sense data, which when pulsed will latch into the Storage Data Buffer (SDR). 

The machine raises Storage Select and Storage Use for a memory cycle. It then alternates Storage Read and Storage Write for the two halves of a core memory cycle. The basic machine cycle time of the 1130 is 450 ns and a complete memory cycle takes 8 of them, thus 3.6 us. Modern SRAM and nonvolatile SRAM are so much faster than they could easily be adopted to replace the core memory compartment. Even the faster models of the 1130, at 275 ns basic cycle time, is glacial compared to modern memory chips. 

The 1130 processor sets the address bits before the Storage Select and Storage Use signals are activated. Sometime during the 1.8 us of the read portion, the core memory returns a pulse on the sense lines for any bit of memory that had a 1 value. This latches asynchronously into the SBR. 

When the Storage Write signal is activated, the processor will latch the intended value to write back into the address in the SBR. The data bits sent to core memory are directly from the SBR. This will be finished sometime before the 1.8 us write half of the memory cycle is complete. 

Interfacing would involve a state machine driven by the select and use signals plus the read or write signal. It would trigger a read during the read time, wait long enough to be sure that valid data is available on the output of the SRAM, and then produce pulses on any sense line where a 1 bit was retrieved. 

Similarly, for the write portion of the cycle, it would take the SBR value and present it to the chip, with a write enable to the chip long enough for its write cycle time. No status need be returned to the 1130. 

In fact, the 1130 has no control or status signals coming back from core storage. It clears the SBR to zeroes, sets the control signals to the core memory compartment and then at the appropriate time it examines the SBR. Any sense pulses that arrived will latch into the SBR. Parity checking is done three quarters of the way through the memory cycle, midway through the write half. 

If the machine is not updating the memory location with a new value, then the SBR will retain the value that was latched in during the read. If updating the SBR with new content, for example data coming in from a peripheral such as a card reader, then the machine parity checks the replaced value instead of the originally read value. 

The SJ-4 memory (3.6us) used with the 450 ns cycle time machine returns the sense pulses somewhere around 800 ns after the start of the read cycle. The write operation is considered to take place 800 ns after the start of the write cycle. 

The SJ-2 memory (2.2 us) used with the 275 ns cycle time machines would have read and write times of approximately 500 ns. Still achievable with a 100 ns SRAM device, but if timing got tight then 70 ns chips are available at a somewhat higher price. 

REASONABLE DEVICES AVAILABLE

The 32K x 8 bit DS1330Y nonvolatile chip will cost around $12 per chip for 100 ns speed ratings. It also requires a lithium battery cap to provide the nonvolatile data for 10+ years, after which the cap can be replacing during system operation to ensure continued data protection. 

For the 1130 usage, 16 bit data words plus two parity bits, this would need to read or write three bytes for each 1130 access, which is still far faster than a single 1130 basic clock cycle. It would be a bit wasteful of capacity, giving us 8K 16 bit words plus 8K of 2 bit parity. Using just over 56% of the bit capacity doesn't bother me given the low cost of the chip, it is just inelegant.